Stacked Die Processes

Some stacked die applications contain flip chip interconnection.

The die is normally bumped with gold stud bumps. The bumped die can be connected to the substrate using thermal compression bonding, thermosonic bonding, non-conductive adhesive or conductive adhesive. Gold bumps are bonded to the die using a modified wire bonder, such as the K&S AT Premier^TM,  capable of handling various wafer sizes and equipped with special bumping software. The shape of the gold stud bump can be optimized per application and attachment methods.

Thermal compression and thermosonic bonding are often limited to low and medium pin count devices.  Non-conductive and conductive adhesives are more attractive for high pin count, larger devices due to the lower bond force required per bump and the relatively lower assembly temperature.

Below:  Two examples of a stacked die package with wire bond and flip chip interconnections.

Lower die FC and upper die WB

• Suitable for lower logic die and upper memory, including DRAM.
• No redistribution needed - lower cost variation.
• Substrate required for both FC and WB interconnect.

Lower die WB and upper die FC

• Suitable for higher speed communications between the lower (ASIC) and upper (memory) chips.
• Die are designed for each other: lower die redistribution.